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chirpzee
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 Posted: Thu Nov 20, 2008 2:06 am Post subject: xilinx dds v5.0 instantiation |
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hello. i'm new to fpga programming and am looking to implement a DDS in a
virtex II as part of a DDC. i have ise 10.1 and am looking for any help or
examples of instantiating and the timing required to change the frequency
(pinc) of the DDS. i have used the coregen tool to create what i think is
a correct DDS module, and i get no compiler errors when i instantiate the
device and compile. here's my code for declaration and instantiation:
--component declaration
component trydds1
port
(
DATA: in std_logic_vector(31 downto 0);
WE: in std_logic;
A: in std_logic_vector(4 downto 0);
CLK: in std_logic;
SCLR : in std_logic;
RFD: out std_logic;
RDY: out std_logic;
SINE: out std_logic_vector(15 downto 0);
COSINE: out std_logic_vector(15 downto 0)
);
end component; |
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langwadt@fonz.dk
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| Posted: Thu Nov 20, 2008 2:06 am Post subject: Re: xilinx dds v5.0 instantiation |
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On 19 Nov., 21:06, "chirpzee" <david_car...@yahoo.com> wrote:
| Quote: | hello. i'm new to fpga programming and am looking to implement a DDS in a
virtex II as part of a DDC. i have ise 10.1 and am looking for any help or
examples of instantiating and the timing required to change the frequency
(pinc) of the DDS. i have used the coregen tool to create what i think is
a correct DDS module, and i get no compiler errors when i instantiate the
device and compile. here's my code for declaration and instantiation:
--component declaration
component trydds1
port
(
DATA: in std_logic_vector(31 downto 0);
WE: in std_logic;
A: in std_logic_vector(4 downto 0);
CLK: in std_logic;
SCLR : in std_logic;
RFD: out std_logic;
RDY: out std_logic;
SINE: out std_logic_vector(15 downto 0);
COSINE: out std_logic_vector(15 downto 0)
);
end component;
|
when you generated the dds, coregen made a *.vho file that you shows
how to instantiate it
-Lasse |
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