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John Larkin
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 Posted: Wed Aug 27, 2008 6:51 am Post subject: Re: need fast FPGA suggestions |
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On Tue, 26 Aug 2008 12:56:50 -0500, Jon Elson <elson@wustl.edu> wrote:
| Quote: |
John Larkin wrote:
You can do coarse delays by counting at some modest clock frequency,
and get fine delays from a fast-clocked shift register or a simple
external analog vernier. The analog thing can take you down to
picosecond resolution.
You can also double resolution by using both clock edges.
But can you tolerate the 1-clock p-p jitter that you'll get from
asynchronous trigger inputs slamming into a continuous clock?
I didn't think so, that's why I designed a hideous analog delay circuit,
much like the no-longer-available-at-a-sane-price AD9501. (A current
source,
integrating cap, comparator and DAC) I ended up with 1200 components on
one board for 64 of these delay circuits. And, it uses the difficult to
mount AD CMP603 in the 3 mm square CSP that gave me FITS getting a
couple boards working. Many, many, many shorts and opens!
But, aparently, 2 ns of jitter is NOT a problem. Only the initial delay
will suffer the jitter, the width of the second timer will always be
synched to the clock, and so the width won't vary. That was the more
critical part of it.
I'm still researching how you do this with the DDR feature.
Jon
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You might consider this trick: when a trigger comes in, start an
oscillator, and use that to clock the FPGA. Then time out with
counters, and use some fractional-clock trick if you need sub-clock
delay or width resolution.
I've done this with LC oscillators and coaxial ceramic resonator
oscillators; both can be started essentially instantly and can have
pretty good jitter performance. The resulting FPGA logic can be pretty
simple.
John |
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Jim Granville
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| Posted: Wed Aug 27, 2008 3:36 pm Post subject: Re: need fast FPGA suggestions |
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John McCaskill wrote:
| Quote: | The Virtex 4 family has input and output SERDES on their IOs. These
are not the MGTs of the FX version, and are on all versions of the
Virtex 4s. The SERDES can be used with the DDR registers in the IOB to
get even faster performance from them. The SERDES can also be used in
pairs to get a larger parallel to serial ratio.
snip |
SERDES are on more devices these days, and are the obvious and simple'
way to get extended timing.
If the price/package excludes those, you can use multiple phase clocks
to interpolate time : generate as many phases as the device/DLLs
can, and capture, then feed into a priority encoder to get a
Phase Location, and then on output, a similar converse PhaseSum is used
for fractional clock times. More logic, but lower clock speeds.
-jg |
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John_H
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| Posted: Wed Aug 27, 2008 11:10 pm Post subject: Re: need fast FPGA suggestions |
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On Aug 27, 2:45 pm, Jon Elson <el...@wustl.edu> wrote:
| Quote: |
Yes, I think you are right, and I greatly appreciate the data points
about the 206 MHz and the 10-bit carry. The circuit I need to implement
is REALLY simple, but gets a bit more complicated when you add in the
logic to handle the DDR. The SERDES components in the Virtex look like
they would be ideal to handle this, and instead of only having an X2
option with DDR, this makes an X8 option nearly as simple. The part
cost, all by itself, is not that terrible, the smaller Virtex chips are
around $200. The other problem, however, is we have no capability or
experience with BGAs, and would have to send them out. That at least
doubles the cost!
Thanks again for the info!
|
1) The Virtex is a good way to go; the SERDES will work for you as
long as your minimum delays are met (same is true of shorter delay DDR
version).
2) I thought you had 32 channels
3) One instantiation is almost the same as 64 in complexity. It's one
lone module that produces the results for each instance.
4) BGAs can give growing pains, but it's the industry's current sweet-
spot. If not now, than a few more months down the road.
I'd personally be happy to crank out a design like this in the
Spartan3x series, but for a 5-up production the added speed and
functionality of the Virtex is a good win. |
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Jon Elson
Guest
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| Posted: Thu Aug 28, 2008 2:45 am Post subject: Re: need fast FPGA suggestions |
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Andrew FPGA wrote:
| Quote: | So, you think a 13-bit counter feeding a 13-bit identity comparator will
work at 250 MHz?
Others have said it may be possible but what they fail to acknowledge
is the large amount of extra design effort and care required to get
there. 250 MHz is really pushing the limits in spartan 3e in my
experience. You may have to work very hard to get there: for example I
have just finished a distributed arithmetic filter design, that has
only 1 LUT level between flops and after a lot of effort I got it to
run at 206 MHz in a sp3 1600e. I can see how to get to 220MHz, but
beyond that I don't know. The longest carry chain is 10 bits.
I had to bypass synthesis and instantiate xilinx primitives directly
to gaurantee my logic was implemented in 1 LUT level. Then I had to
manually floorplan the design - placing each flop with the
corresponding LUT by hand( I uses RLOC's embedded in the VHDL source).
The automatic placer didn't always place the LUT with the FLOP so you
end up with 2 routes which kills the timing completely.
Yes, with 64 instantiations of the circuit on the FPGA, I really DON'T |
want to deal with this!
| Quote: |
Yeah, I really don't think we can handle $2000 IC's. This isn't a real
production project, we might build 5 of them at a time, but we are still
cost-sensitive.
If its such low volumes just take the unit cost hit and move to a
Virtex part. How valuable is your time?
|
Yes, I think you are right, and I greatly appreciate the data points
about the 206 MHz and the 10-bit carry. The circuit I need to implement
is REALLY simple, but gets a bit more complicated when you add in the
logic to handle the DDR. The SERDES components in the Virtex look like
they would be ideal to handle this, and instead of only having an X2
option with DDR, this makes an X8 option nearly as simple. The part
cost, all by itself, is not that terrible, the smaller Virtex chips are
around $200. The other problem, however, is we have no capability or
experience with BGAs, and would have to send them out. That at least
doubles the cost!
Thanks again for the info!
Jon |
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Jon Elson
Guest
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| Posted: Thu Aug 28, 2008 2:53 am Post subject: Re: need fast FPGA suggestions |
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John McCaskill wrote:
| Quote: | I was not clear if you needed a minimum delay of 10ns, a minimum pulse
width or 10 ns, or both. If you need a minimum delay of 10 ns, you
would need to run a smaller ratio to get your parallel clock fast
enough.
Yes, as soon as you mentioned the SERDES in a previous message, I |
realized this was the best scheme for Virtex 4. I think trying to use
Spartan 3E at insane clock rates would be risky, and might lead to a
total collapse of the automatic tools when they try to route 64
instances of this module per chip. I don't want to have to do what
Andrew ran into with manual placing x64 times. No FUN!
| Quote: | Take a look at the Virtex-4 users guide section on the ISERDES and
OSERDES for more information about them:
http://www.xilinx.com/support/documentation/user_guides/ug070.pdf
I also noted that you did not like that they came in BGAs. We have
used out side rework shops to place BGAs for us with good results. If
I remember correctly, it cost under $100 USD each for just a few
boards. I recommend http://www.process-sciences.com/services/default.asp
The outfits I've seen so far seem to have a high setup charge, which makes |
them roughly double the component price. There likely are shops with
better rates for small jobs.
Jon |
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Jon Elson
Guest
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| Posted: Thu Aug 28, 2008 2:54 am Post subject: Re: need fast FPGA suggestions |
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John Larkin wrote:
| Quote: | You might consider this trick: when a trigger comes in, start an
oscillator, and use that to clock the FPGA. Then time out with
counters, and use some fractional-clock trick if you need sub-clock
delay or width resolution.
I've done this with LC oscillators and coaxial ceramic resonator
oscillators; both can be started essentially instantly and can have
pretty good jitter performance. The resulting FPGA logic can be pretty
simple.
But, we have 32 independent inputs, with no time correlation. Not |
enough global clock trees to handle that.
Jon |
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Jim Granville
Guest
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| Posted: Thu Aug 28, 2008 4:52 am Post subject: Re: need fast FPGA suggestions |
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Jon Elson wrote:
| Quote: | Yes, I think you are right, and I greatly appreciate the data points
about the 206 MHz and the 10-bit carry. The circuit I need to implement
is REALLY simple, but gets a bit more complicated when you add in the
logic to handle the DDR. The SERDES components in the Virtex look like
they would be ideal to handle this, and instead of only having an X2
option with DDR, this makes an X8 option nearly as simple. The part
cost, all by itself, is not that terrible, the smaller Virtex chips are
around $200. The other problem, however, is we have no capability or
experience with BGAs, and would have to send them out. That at least
doubles the cost!
|
Lattice claim to have lowest cost SERDES - but I'm not sure anyone
does SERDES in non-BGA packages...
Could you target a low cost Eval Board - as a 'FPGA module' ?
-jg |
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Rob Gaddi
Guest
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| Posted: Thu Aug 28, 2008 5:03 am Post subject: Re: need fast FPGA suggestions |
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Regarding the long counters at 250 MHz: I've only worked with Spartan 3s, not the Virtexes, but I was under the impression that the DSP48 blocks tend to be built for this sort of thing. Granted, using a full MAC block as a counter (possibly a down counter) seems to be overkill, but I can't see where you'd need them for anything else.
--
Rob Gaddi, Highland Technology
Email address is currently out of order
On Wed, 27 Aug 2008 16:10:21 -0700 (PDT)
John_H <newsgroup@johnhandwork.com> wrote:
| Quote: | On Aug 27, 2:45 pm, Jon Elson <el...@wustl.edu> wrote:
Yes, I think you are right, and I greatly appreciate the data points
about the 206 MHz and the 10-bit carry. The circuit I need to implement
is REALLY simple, but gets a bit more complicated when you add in the
logic to handle the DDR. The SERDES components in the Virtex look like
they would be ideal to handle this, and instead of only having an X2
option with DDR, this makes an X8 option nearly as simple. The part
cost, all by itself, is not that terrible, the smaller Virtex chips are
around $200. The other problem, however, is we have no capability or
experience with BGAs, and would have to send them out. That at least
doubles the cost!
Thanks again for the info!
1) The Virtex is a good way to go; the SERDES will work for you as
long as your minimum delays are met (same is true of shorter delay DDR
version).
2) I thought you had 32 channels
3) One instantiation is almost the same as 64 in complexity. It's one
lone module that produces the results for each instance.
4) BGAs can give growing pains, but it's the industry's current sweet-
spot. If not now, than a few more months down the road.
I'd personally be happy to crank out a design like this in the
Spartan3x series, but for a 5-up production the added speed and
functionality of the Virtex is a good win. |
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John Larkin
Guest
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| Posted: Thu Aug 28, 2008 5:06 am Post subject: Re: need fast FPGA suggestions |
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On Wed, 27 Aug 2008 16:54:55 -0500, Jon Elson <elson@wustl.edu> wrote:
| Quote: |
John Larkin wrote:
You might consider this trick: when a trigger comes in, start an
oscillator, and use that to clock the FPGA. Then time out with
counters, and use some fractional-clock trick if you need sub-clock
delay or width resolution.
I've done this with LC oscillators and coaxial ceramic resonator
oscillators; both can be started essentially instantly and can have
pretty good jitter performance. The resulting FPGA logic can be pretty
simple.
But, we have 32 independent inputs, with no time correlation. Not
enough global clock trees to handle that.
Jon
|
Oh, 32 separate triggers. Stick with analog ramps?
Some of the LVDS line receivers make might fine fast and cheap
comparators, duals even. So could probably do it all in cmos these
days, fairly simple stuff.
Trigger fires flipflop, turns ramp loose; ramp drives two comparators,
which drive a logic gate to make rising/falling output edges. 2nd
comparator clears flipflop. 64 DAC channels program the mess, not bad
if you use serial octal dacs. Figure 2 square inches per channel to be
generous, so it's an 8x8" board.
John |
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Jim Granville
Guest
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| Posted: Thu Aug 28, 2008 6:06 am Post subject: Re: need fast FPGA suggestions |
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John Larkin wrote:
| Quote: | Oh, 32 separate triggers. Stick with analog ramps?
Some of the LVDS line receivers make might fine fast and cheap
comparators, duals even. So could probably do it all in cmos these
days, fairly simple stuff.
Trigger fires flipflop, turns ramp loose; ramp drives two comparators,
which drive a logic gate to make rising/falling output edges. 2nd
comparator clears flipflop. 64 DAC channels program the mess, not bad
if you use serial octal dacs. Figure 2 square inches per channel to be
generous, so it's an 8x8" board.
|
Analog is a candidate, but the OP mentioned a 100:1 dynamic range.
Maybe some range-sw caps ?
Anyone seen Vos vs Common Mode voltage plots for LVDS channels
in FPGAs ? Cross talk figures ?
-jg |
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John Larkin
Guest
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| Posted: Thu Aug 28, 2008 7:03 am Post subject: Re: need fast FPGA suggestions |
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On Thu, 28 Aug 2008 13:06:02 +1200, Jim Granville
<no.spam@designtools.maps.co.nz> wrote:
| Quote: | John Larkin wrote:
Oh, 32 separate triggers. Stick with analog ramps?
Some of the LVDS line receivers make might fine fast and cheap
comparators, duals even. So could probably do it all in cmos these
days, fairly simple stuff.
Trigger fires flipflop, turns ramp loose; ramp drives two comparators,
which drive a logic gate to make rising/falling output edges. 2nd
comparator clears flipflop. 64 DAC channels program the mess, not bad
if you use serial octal dacs. Figure 2 square inches per channel to be
generous, so it's an 8x8" board.
Analog is a candidate, but the OP mentioned a 100:1 dynamic range.
Maybe some range-sw caps ?
Anyone seen Vos vs Common Mode voltage plots for LVDS channels
in FPGAs ? Cross talk figures ?
-jg
|
We did some experiments on Spartan 3's, running Vccio at 3.3 to 3.5
volts. It sure looked like the LVDS inputs were good
almost-rail-to-rail comparators. I was impressed.
We didn't measure Vos, as we were just interested in using them as the
comparators in analog ramp circuits, to generate sub-ns tunable
delays, and we assumed we'd calibrate out any offsets. Linear analog
ramp goes onto one side of an lvds input, dac driving the other side.
We did find that they have a lot of jitter when the compare happens
anywhere near the edge of any of the on-chip clocks. With a bunch of,
say, 25 ns ramps coming in, you might expect pretty good jitter, 40 ps
RMS maybe, but with delay zones that peak in the 100 ps range as a
result of crosstalk from clocks or adjacent channels. Not too bad, but
it wasn't good enough for our applications.
John |
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rickman
Guest
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| Posted: Thu Aug 28, 2008 3:30 pm Post subject: Re: need fast FPGA suggestions |
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On Aug 27, 5:45 pm, Jon Elson <el...@wustl.edu> wrote:
| Quote: | Andrew FPGA wrote:
So, you think a 13-bit counter feeding a 13-bit identity comparator will
work at 250 MHz?
Others have said it may be possible but what they fail to acknowledge
is the large amount of extra design effort and care required to get
there. 250 MHz is really pushing the limits in spartan 3e in my
experience. You may have to work very hard to get there: for example I
have just finished a distributed arithmetic filter design, that has
only 1 LUT level between flops and after a lot of effort I got it to
run at 206 MHz in a sp3 1600e. I can see how to get to 220MHz, but
beyond that I don't know. The longest carry chain is 10 bits.
I had to bypass synthesis and instantiate xilinx primitives directly
to gaurantee my logic was implemented in 1 LUT level. Then I had to
manually floorplan the design - placing each flop with the
corresponding LUT by hand( I uses RLOC's embedded in the VHDL source).
The automatic placer didn't always place the LUT with the FLOP so you
end up with 2 routes which kills the timing completely.
Yes, with 64 instantiations of the circuit on the FPGA, I really DON'T
want to deal with this!
Yeah, I really don't think we can handle $2000 IC's. This isn't a real
production project, we might build 5 of them at a time, but we are still
cost-sensitive.
If its such low volumes just take the unit cost hit and move to a
Virtex part. How valuable is your time?
Yes, I think you are right, and I greatly appreciate the data points
about the 206 MHz and the 10-bit carry. The circuit I need to implement
is REALLY simple, but gets a bit more complicated when you add in the
logic to handle the DDR. The SERDES components in the Virtex look like
they would be ideal to handle this, and instead of only having an X2
option with DDR, this makes an X8 option nearly as simple. The part
cost, all by itself, is not that terrible, the smaller Virtex chips are
around $200. The other problem, however, is we have no capability or
experience with BGAs, and would have to send them out. That at least
doubles the cost!
|
You don't have to use Virtex to get SERDES. The low cost Lattice
family has SERDES and should be able to do what you are looking for at
a *much* lower price.
Rick |
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John_H
Guest
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| Posted: Thu Aug 28, 2008 7:11 pm Post subject: Re: need fast FPGA suggestions |
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On Aug 28, 8:30 am, rickman <gnu...@gmail.com> wrote:
| Quote: |
You don't have to use Virtex to get SERDES. The low cost Lattice
family has SERDES and should be able to do what you are looking for at
a *much* lower price.
|
While it's true the 3+Gb/s high speed serial channels are available in
the Lattice parts (my first Lattice design has started in the ECP2M -
yay!) the SERDES referred to in the Virtex parts for these posts are -
unless I'm sincerely mistaken - the serializer/deserializer elements
built into the general IOBs. The standard I/Os end up with 800Mb/
s-1Gb/s data rates (pulling these numbers from memory) with a simpler
interface than the MGTs or similar RocketIO that can far exceed the
general I/O data rates.
Even in the lattice part, 32 channels of receive and 32 channels of
transmit is costly in the 3Gb/s SERDES channels.
- John_H |
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Jon Elson
Guest
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| Posted: Thu Aug 28, 2008 9:01 pm Post subject: Re: need fast FPGA suggestions |
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John_H wrote:
| Quote: | On Aug 27, 2:45 pm, Jon Elson <el...@wustl.edu> wrote:
Yes, I think you are right, and I greatly appreciate the data points
about the 206 MHz and the 10-bit carry. The circuit I need to implement
is REALLY simple, but gets a bit more complicated when you add in the
logic to handle the DDR. The SERDES components in the Virtex look like
they would be ideal to handle this, and instead of only having an X2
option with DDR, this makes an X8 option nearly as simple. The part
cost, all by itself, is not that terrible, the smaller Virtex chips are
around $200. The other problem, however, is we have no capability or
experience with BGAs, and would have to send them out. That at least
doubles the cost!
Thanks again for the info!
1) The Virtex is a good way to go; the SERDES will work for you as
long as your minimum delays are met (same is true of shorter delay DDR
version).
2) I thought you had 32 channels
What we have is 32 inputs. Each input starts an independent and |
individually adjustable delay, at the end of that delay a pulse of a
settable width comes out. So, the delay and the width circuit are
essentially digital one-shots, and basically the same. The only
difference would be the delay has an asynchronous input, the width is
totally synchronous.
| Quote: | 3) One instantiation is almost the same as 64 in complexity. It's one
lone module that produces the results for each instance.
As long as you don't need to go into the chip viewer and manually route |
anything to meet timing, yes. I REALLY do not want to have to do that,
as Andrew apparently needed to do on a Spartan 3 project.
| Quote: | 4) BGAs can give growing pains, but it's the industry's current sweet-
spot. If not now, than a few more months down the road.
I'd personally be happy to crank out a design like this in the
Spartan3x series, but for a 5-up production the added speed and
functionality of the Virtex is a good win.
|
Well, given the serdes function of the Virtex, maybe we can go 1 ns
input and output resolution, with only 125 MHz clock on the
counter/comparator. My boss would really love that. The smaller Virtex
seem to come in a 1mm-pitch BGA, maybe I can even learn how to do that
myself. Since the balls are only around the perimiter, it might be
visibly inspectable. I'll have to do more research to find out what is
practical.
Jon |
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Jon Elson
Guest
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| Posted: Thu Aug 28, 2008 9:06 pm Post subject: Re: need fast FPGA suggestions |
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Jim Granville wrote:
| Quote: | John Larkin wrote:
Oh, 32 separate triggers. Stick with analog ramps?
Some of the LVDS line receivers make might fine fast and cheap
comparators, duals even. So could probably do it all in cmos these
days, fairly simple stuff.
Trigger fires flipflop, turns ramp loose; ramp drives two comparators,
which drive a logic gate to make rising/falling output edges. 2nd
comparator clears flipflop. 64 DAC channels program the mess, not bad
if you use serial octal dacs. Figure 2 square inches per channel to be
generous, so it's an 8x8" board.
Analog is a candidate, but the OP mentioned a 100:1 dynamic range.
Maybe some range-sw caps ?
Well, it is all designed and the board is layed out. I used the AD |
CMP603 single fast comparator. A bear to mount, but a very fine chip
for the purpose. It DOES use 2 range switching caps, plus stray
capacitance as the lowest cap value, plus 2 selections of
current-programming resistor.
THEN, my boss said -- "Hey, couldn't you do that with an FPGA?"
| Quote: | Anyone seen Vos vs Common Mode voltage plots for LVDS channels
in FPGAs ? Cross talk figures ?
I guess you could measure it yourself. |
Jon |
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