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axalay
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 Posted: Fri Nov 14, 2008 7:14 am Post subject: Number of GCLKs: 9 out of 8 112% (OVERMAPPED) |
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I have this problem. Use ISE 9.2 SP4. This problem is solved in ISE
10.1 SP1, but I whant solve this problem in 9.2. Help!!!!  |
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KJ
Guest
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| Posted: Fri Nov 14, 2008 12:54 pm Post subject: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED) |
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On Nov 14, 2:14 am, axalay <axa...@gmail.com> wrote:
| Quote: | I have this problem. Use ISE 9.2 SP4. This problem is solved in ISE
10.1 SP1, but I whant solve this problem in 9.2. Help!!!!
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I'd suggest getting rid of at least one clock.
KJ |
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LittleAlex
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| Posted: Fri Nov 14, 2008 4:11 pm Post subject: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED) |
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On Nov 14, 5:54 am, KJ <kkjenni...@sbcglobal.net> wrote:
| Quote: | On Nov 14, 2:14 am, axalay <axa...@gmail.com> wrote:
I have this problem. Use ISE 9.2 SP4. This problem is solved in ISE
10.1 SP1, but I whant solve this problem in 9.2. Help!!!! :)
I'd suggest getting rid of at least one clock.
KJ
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Or use ISE 10.1. Or both, or all 3!
Build using 10.1. Notice which clocks are assigned to GCLKs. Find
out which of the 9 clocks (from ISE 9.2) are NOT assigned to GCLKs.
Manually assign the 8 favorite clocks to GCLKs.
Disable the option to 'automatically promote to GCLK' or whatever it's
called. It moves around from version to version.
It looks like Xilinx finally addressed the issue where more nets would
be promoted to GCLKs than there were GCLKs available. Previously,
GCLK_max was set according to the family, and was not adjusted for the
particular chip used. I had fun with this one when I did a XC2V4000 -
| Quote: | XC2V3000 migration.
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Where's Peter when we really need him? ;)
PS: KJ has a very valid point. 9 clocks is a LOT of clocks, you can
probably cut this number in half by using gated clocks where
appropriate. |
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LittleAlex
Guest
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| Posted: Sat Nov 15, 2008 12:01 am Post subject: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED) |
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On Nov 14, 2:53 pm, Paul Urbanus <urbpub...@hotmail.com> wrote:
| Quote: |
Probably just a matter of semantics, but gated clocks should be avoided
like the plague for synchronous designs. Presumably you meant using
clock enables where appropriate.
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You are correct. |
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Paul Urbanus
Guest
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| Posted: Sat Nov 15, 2008 4:53 am Post subject: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED) |
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LittleAlex wrote:
| Quote: | On Nov 14, 5:54 am, KJ <kkjenni...@sbcglobal.net> wrote:
On Nov 14, 2:14 am, axalay <axa...@gmail.com> wrote:
I have this problem. Use ISE 9.2 SP4. This problem is solved in ISE
10.1 SP1, but I whant solve this problem in 9.2. Help!!!!
I'd suggest getting rid of at least one clock.
KJ
Or use ISE 10.1. Or both, or all 3!
Build using 10.1. Notice which clocks are assigned to GCLKs. Find
out which of the 9 clocks (from ISE 9.2) are NOT assigned to GCLKs.
Manually assign the 8 favorite clocks to GCLKs.
Disable the option to 'automatically promote to GCLK' or whatever it's
called. It moves around from version to version.
It looks like Xilinx finally addressed the issue where more nets would
be promoted to GCLKs than there were GCLKs available. Previously,
GCLK_max was set according to the family, and was not adjusted for the
particular chip used. I had fun with this one when I did a XC2V4000 -
XC2V3000 migration.
Where's Peter when we really need him? ;)
PS: KJ has a very valid point. 9 clocks is a LOT of clocks, you can
probably cut this number in half by using gated clocks where
appropriate.
|
Probably just a matter of semantics, but gated clocks shoud be avoided
like the plague for synchronous designs. Presumably you meant using
clock enables where appropriate. |
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axalay
Guest
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| Posted: Mon Nov 17, 2008 8:01 am Post subject: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED) |
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On 14 ÎÏÑÂ, 19:11, LittleAlex <alex.lo...@email.com> wrote:
| Quote: | On Nov 14, 5:54 am, KJ <kkjenni...@sbcglobal.net> wrote:
On Nov 14, 2:14 am, axalay <axa...@gmail.com> wrote:
šI have this problem. Use ISE 9.2 SP4. This problem is solved in ISE
10.1 SP1, but I whant solve this problem in 9.2. Help!!!! :)
I'd suggest getting rid of at least one clock.
KJ
Or use ISE 10.1. šOr both, or all 3!
Build using 10.1. šNotice which clocks are assigned to GCLKs. šFind
out which of the 9 clocks (from ISE 9.2) are NOT assigned to GCLKs.
Manually assign the 8 favorite clocks to GCLKs.
Disable the option to 'automatically promote to GCLK' or whatever it's
called. šIt moves around from version to version.
It looks like Xilinx finally addressed the issue where more nets would
be promoted to GCLKs than there were GCLKs available. šPreviously,
GCLK_max was set according to the family, and was not adjusted for the
particular chip used. šI had fun with this one when I did a XC2V4000 -
XC2V3000 migration.
Where's Peter when we really need him? š;)
PS: šKJ has a very valid point. š9 clocks is a LOT of clocks, you can
probably cut this number in half by using gated clocks where
appropriate.
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In ucf I write:
NET "Phy0TxClk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "Phy0RxClk" CLOCK_DEDICATED_ROUTE = FALSE;
But in ISE9.2 it give error:
Applying constraints in "system_stub.ucf" to the design...
ERROR:NgdBuild:789 - "system_stub.ucf" Line 86:
'CLOCK_DEDICATED_ROUTE' is an
invalid constraint name.
ERROR:NgdBuild:789 - "system_stub.ucf" Line 87:
'CLOCK_DEDICATED_ROUTE' is an
invalid constraint name.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file
"system_stub.ucf". |
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axalay
Guest
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| Posted: Mon Nov 17, 2008 8:06 am Post subject: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED) |
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On 15 ÎÏÑÂ, 01:53, Paul Urbanus <urbpub...@hotmail.com> wrote:
| Quote: | LittleAlex wrote:
On Nov 14, 5:54 am, KJ <kkjenni...@sbcglobal.net> wrote:
On Nov 14, 2:14 am, axalay <axa...@gmail.com> wrote:
šI have this problem. Use ISE 9.2 SP4. This problem is solved in ISE
10.1 SP1, but I whant solve this problem in 9.2. Help!!!!
I'd suggest getting rid of at least one clock.
KJ
Or use ISE 10.1. šOr both, or all 3!
Build using 10.1. šNotice which clocks are assigned to GCLKs. šFind
out which of the 9 clocks (from ISE 9.2) are NOT assigned to GCLKs.
Manually assign the 8 favorite clocks to GCLKs.
Disable the option to 'automatically promote to GCLK' or whatever it's
called. šIt moves around from version to version.
It looks like Xilinx finally addressed the issue where more nets would
be promoted to GCLKs than there were GCLKs available. šPreviously,
GCLK_max was set according to the family, and was not adjusted for the
particular chip used. šI had fun with this one when I did a XC2V4000 -
XC2V3000 migration.
Where's Peter when we really need him? š;)
PS: šKJ has a very valid point. š9 clocks is a LOT of clocks, you can
probably cut this number in half by using gated clocks where
appropriate.
Probably just a matter of semantics, but gated clocks shoud be avoided
like the plague for synchronous designs. Presumably you meant using
clock enables where appropriate.- óËÒÙÔØ ÃÉÔÉÒÕÅÍÙÊ ÔÅËÓÔ -
- ðÏËÁÚÁÔØ ÃÉÔÉÒÕÅÍÙÊ ÔÅËÓÔ -
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In my project I have many input clocks. But I dont whant connect that
to GCLK. I write in UCF file that:
NET "Phy0TxClk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "Phy0RxClk" CLOCK_DEDICATED_ROUTE = FALSE;
But translare report: invalid constraint name |
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Brian Drummond
Guest
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| Posted: Mon Nov 17, 2008 5:15 pm Post subject: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED) |
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On Mon, 17 Nov 2008 00:01:11 -0800 (PST), axalay <axalay@gmail.com>
wrote:
| Quote: |
In ucf I write:
NET "Phy0TxClk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "Phy0RxClk" CLOCK_DEDICATED_ROUTE = FALSE;
But in ISE9.2 it give error:
Applying constraints in "system_stub.ucf" to the design...
ERROR:NgdBuild:789 - "system_stub.ucf" Line 86:
'CLOCK_DEDICATED_ROUTE' is an
invalid constraint name.
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I think this AR adresses that issue...
http://www.xilinx.com/support/answers/30355.htm
That constraint is apparently new since ISE9.2. The AR mentions an older
method which was used with 9.2
- Brian |
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