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How to run Assura DRC from Command line? Reotaro Hashemoto 4 5 Thu Jan 08, 2009 11:45 pm
Concatenate two waveforms mm77 2 0 Thu Jan 08, 2009 10:52 pm
Assura LVS problem Adam 6 0 Thu Jan 08, 2009 5:36 pm
Creating combined libraries Roger Light 2 8 Wed Jan 07, 2009 9:52 pm
Skill -- Automizing layout. sridhartv25@gmail.com 5 0 Wed Jan 07, 2009 8:37 pm
converting a rectilinear polygon to rectangle polygons layoutDesign 1 0 Wed Jan 07, 2009 9:45 am
Replace flat vias with symbolic vias The Master 1 4 Mon Jan 05, 2009 8:14 pm
Need to know the list of layers used in Virtuoso layout desi Vitalie 5 7 Mon Jan 05, 2009 7:55 pm
Creating a new category in a giving library nour 5 10 Mon Jan 05, 2009 7:43 pm
what do these noise params mean? yanfei 3 5 Mon Jan 05, 2009 7:38 pm
can't get custom cellview to work Guest 1 10 Fri Jan 02, 2009 8:59 am
easy way to copy pin and text display in Skill?? vlsidesign 5 15 Fri Jan 02, 2009 8:58 am
How to trigger Pcell cdfs vtcad 1 7 Fri Jan 02, 2009 8:58 am
Unable to create new cell view Guest 1 9 Thu Jan 01, 2009 5:36 pm
Process X values in Parametric plot Guest 1 5 Thu Jan 01, 2009 5:13 pm
cdlout and pinMap option: why netlist is different ??? bu-bu 1 8 Thu Jan 01, 2009 3:24 pm
how to create a form to open a GUI ? Juve 1 5 Thu Jan 01, 2009 3:12 pm
Avoid "_" when expanding busses during hspice netlisting Guest 1 5 Thu Jan 01, 2009 3:09 pm
Skill Layout Guest 3 7 Thu Jan 01, 2009 8:38 am
node capacitance in SpectreMDL J. Patrick Bedell 1 5 Thu Jan 01, 2009 8:38 am
Skill program sridhartv25@gmail.com 7 11 Thu Jan 01, 2009 8:38 am
*Error* ddGetObjReadPath: argument #1 should be a ddUserType rover8898 1 5 Wed Dec 31, 2008 3:40 pm
Unable to access Layout XL in cadence shilpi 1 5 Wed Dec 31, 2008 2:57 pm
What's the function of file *.cbe? Guest 1 4 Wed Dec 31, 2008 8:54 am
loading ADE state from skill Jonno loves Apple Pie 2 5 Mon Dec 29, 2008 4:19 pm
moving via pcells to the topmost level SS 1 1 Wed Dec 24, 2008 4:08 pm
Verilog-2001 tool support: spotty at best? 1 ... 11 , 12 , 13 ] server 183 17 Tue Dec 23, 2008 9:20 pm
Place all the cells of the library (like standard cell lib) Juve 2 2 Tue Dec 23, 2008 2:37 pm
Find the technology name The Master 2 7 Sat Dec 20, 2008 6:34 pm
How to use skill command to close a schematic window? Guest 3 4 Sat Dec 20, 2008 6:32 pm
Problems in opening OSU std cells for PDK45nm in virtuoso Koustav 2 6 Sat Dec 20, 2008 4:45 pm
Cadence IC 6.1 Form Placement eyn 2 7 Sat Dec 20, 2008 4:42 pm
Plotting transistor parameters against time spectrallypure 3 4 Sat Dec 20, 2008 4:35 pm
Cadence 5.14 support until 12/2009 ? (for Beckett-san and ot bu-bu 2 1 Sat Dec 20, 2008 4:33 pm
Searching Nets SS 1 4 Sat Dec 20, 2008 8:55 am
menu and nesting/bindkeys Guest 6 7 Sat Dec 20, 2008 8:55 am
Getting Analog Design Environment to reread model files Randy Yates 3 4 Sat Dec 20, 2008 8:55 am
Control is not coming out from leHiCreatePath() fn due to ne Pratheesh.s 2 4 Sat Dec 20, 2008 8:55 am
Very Basic Q: Is L Drawn Length or Effective Length? Randy Yates 3 10 Sat Dec 20, 2008 3:17 am
Error in Using Calibre for DRC bearsarebears 2 5 Thu Dec 18, 2008 10:18 am
Creating combined libraries Roger Light 0 2 Tue Dec 16, 2008 7:17 pm
Manual routing in Cadance Lakshman 4 3 Tue Dec 16, 2008 4:39 pm
Create Path Command Guest 4 9 Mon Dec 15, 2008 6:30 pm
Questions about skill manell15 2 11 Mon Dec 15, 2008 12:10 am
skill and tk jimka 5 6 Sun Dec 07, 2008 10:11 pm
Need to find end of path command point in virtouso. Guest 0 2 Fri Dec 05, 2008 5:53 pm
SignalStorm analyses options Guest 0 2 Thu Dec 04, 2008 8:07 am
SKILL context file decompilation jan 2 4 Wed Dec 03, 2008 9:17 pm
Python PCells .. Where to start? Reotaro Hashemoto 1 3 Wed Dec 03, 2008 7:59 am
How to Cadence stdin, stdout Vitalie 1 2 Wed Dec 03, 2008 6:08 am
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